• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    A method of producing a layer of semiconductor material comprising steps of: a) forming a stack comprising a first layer (3) based on a first semiconductor material coated with a second layer (6) based on a second semiconductor material having a mesh parameter different from that of the first semiconductor material, b) forming on the second semiconductor layer a mask (10) having a symmetry, c) making the first layer amorphous semiconductor layer (6) and regions (6 ') of the second semiconductor layer (6) without amorphous rendering one or more regions (6a, 6b, 6c) of the second semiconductor layer protected by the mask and respectively facing the one or more masking blocks d) recrystallizing the amorphous regions (6a, 6b, 6c) and the first semiconductor layer, whereby this first semiconductor layer is constrained (FIG. 1A).
    公开号:FR3041146A1
    申请号:FR1558482
    申请日:2015-09-11
    公开日:2017-03-17
    发明作者:Emmanuel Augendre；Aomar Halimaoui；Sylvain Maitrejean；Shay Reboh
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR TENSIONING A SEMICONDUCTOR FILM
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART
    The present application relates to the field of structures comprising a semiconductor layer having a deformation or mechanical stress.
    By mechanical deformation is meant a material which has its parameter (s) of elongated crystalline mesh (es) or shortened (s) with respect to a nominal mesh parameter.
    In the case where the deformed mesh parameter is larger than the so-called "natural" parameter of the crystalline material, it is said to be in tensive deformation or in tension. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be compressive deformation or compression. To these states of mechanical deformation, one associates states of mechanical stresses. However, it is also common to refer to these deformation states as mechanical stress states. In the remainder of the present application, this notion of strain ("strain" in the English terminology) will be generically referred to as "constraint".
    For certain applications, in particular for producing transistors, it may be advantageous to provide a layer of constrained semiconductor material. A mechanical stress in tension or in compression on a semiconductor layer makes it possible to induce an increase in the speed of the charge carriers. This improves the performance of transistor devices formed in such a layer.
    It is known to produce substrates of semiconductor type constrained on insulator, that is to say in which the material of the semiconducting surface layer is stressed, this surface layer being disposed on an insulating layer, itself disposed on a generally semiconductive support layer.
    The stressed semiconductive surface layer is generally intended to serve as an active layer, that is to say in which at least a portion of electronic components such as transistors is intended to be formed.
    In particular, it is known to produce sSOI substrates (sSOI for "strained Silicon On Insulator" or silicon forced on insulator) having a surface layer of silicon stressed in tension.
    One method for producing such a type of substrate may consist firstly in epitaxially growing a SiGe-based semiconductor layer constrained in compression on an Si-based semiconductor layer. Next, an ion implantation of the Si-based semiconductor layer is carried out. Si layer and a lower region of the SiGe layer so as to relax the SiGe. The lower region of the SiGe layer and the Si layer are then recrystallized using an upper region of the SiGe layer which has not been rendered amorphous and whose crystalline structure has been preserved as starting area at a recrystallization front. During recrystallization, the crystalline SiGe seeds impose their mesh parameter on the Si layer which is then put under tension.
    During the amorphization of SiGe which leads to its relaxation, a creep phenomenon of the amorphous region can appear. This tends to create discontinuities in the upper region of the non-amorphized SiGe layer whose crystal structure has been preserved. This upper region is then formed of crystalline islands distributed randomly. When recrystallization is carried out, island rotation can give rise to crystalline orientation discontinuities in the recrystallized layers. The strained Si layer obtained after recrystallization is then inhomogeneous in terms of crystalline orientation.
    There is the problem of finding a new method for producing a structure having a layer of constrained semiconductor material which is improved with respect to the disadvantages given above.
    STATEMENT OF THE INVENTION
    An embodiment of the present invention provides a method of making a structure comprising a layer of constrained semiconductor material, the method comprising steps of: a) forming on a substrate a stack comprising a first semiconductor layer; conductor based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a mesh parameter different from that of the first semiconductor material, b) producing on the second semiconductor material semiconductor layer of a mask formed of one or more blocks, c) implantations inclined with respect to a normal to the main plane of the substrate, so as to render the first semiconductor layer amorphous and zones of the second layer semiconductor without rendering amorphous one or more regions of the second semiconductor layer protected by the mask and respectively arranged opposite the blocks of the mask, d) recrystallizing the amorphous regions and the first semiconductor layer from which it results that this first semiconductor layer is constrained.
    The mask may have symmetry with respect to a plane of symmetry passing through at least a first block of the mask, this plane of symmetry being orthogonal to a main plane of the substrate.
    By providing a symmetrical distribution of the blocks of the mask, it induces crystallization without rotation of the seed crystals, which allows to implement a semiconductor layer stress of more homogeneous crystalline structure.
    The mask is advantageously formed of several identical blocks arranged in the plane of symmetry in a constant distribution pitch.
    This makes it possible to limit the creep phenomena of amorphous zones and thus participates in obtaining a constrained semiconductor material of better quality.
    Advantageously, the first block is arranged facing a first region of the first semiconductor layer in which a transistor channel is adapted to be produced.
    The channel is thus made in a region remote from the areas in which the recrystallization fronts are likely to meet in step d).
    According to a particular embodiment, the first block may have a pattern similar to that of a transistor gate to be made opposite the first region.
    The mask may be formed by etching at least one layer through block copolymer-based masking.
    According to a particular embodiment, the implantation mask comprises cylinder-shaped blocks whose base extends on the second semiconductor layer. This can make it possible to have a mask whose blocks have a constant distribution pitch in several directions.
    According to another particular embodiment, one or more blocks of the mask have a parallelepipedal shape which extends parallel to the main plane of the substrate and orthogonal to the plane of symmetry. Such a mask shape can allow by amorphization / recrystallization to implement a first semiconductor layer in uni-axial stress.
    The method may further comprise, after recrystallization, a step of removing the second semiconductor layer.
    After removal of the second semiconductor layer, the method may comprise the formation of at least one transistor whose gate is arranged facing the first region and whose channel extends entirely in the first region.
    Advantageously, the first semiconductor layer is silicon, while the second semiconductor layer is silicon germanium.
    The second semiconductor layer may have a germanium concentration gradient, the germanium concentration decreasing as the first layer is approached.
    It is advantageous to provide a second layer with high Germanium concentrations, ie greater than 20% and in particular between 20% and 50% at the level of the face of the second semiconductor layer, which may make it possible to further constrain the first semiconductor layer when it is silicon.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limitative, with reference to the appended drawings in which: FIGS. 1A-1F illustrate an exemplary method for producing a first insulator-constrained semiconductor layer in which this first layer is made amorphous and then recrystallized by imposing on it the mesh parameter of a second semiconductor layer; FIG. 2 illustrates an implementation of a transistor whose channel region extends in the strained semiconductor layer and is provided outside zones in which recrystallization fronts have met during recrystallization; FIG. 3 illustrates an example of an implantation mask having a symmetrical arrangement and formed of cylindrical blocks able to protect certain regions of the second semiconductor layer during amorphization; FIGS. 4A-4C illustrate an alternative method in which the implantation mask has a configuration that is favorable for the creation of a uni-axial stress in the first semiconductor layer;
    Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    In addition, in the description below, terms such as "lower", "higher" which depend on the orientation of the structure apply considering that the structure is oriented as illustrated in the figures.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    An exemplary method for producing a structure with a layer of constrained semiconductor material will now be given in connection with FIGS. 1A-1F.
    The starting material of this process may be a semiconductor-on-insulator substrate 1, in particular an SOI substrate comprising a layer 2 of semi-conducting support, for example made of Si, coated with an insulating layer 3 called BOX (for " Burried Oxide "), itself coated with a superficial semiconductor layer 4, for example based on Si, intended to be stressed, and which will be called the first semiconductor layer.
    On the first semiconductor layer 4 is then grown by epitaxy a second semiconductor layer 6 based on a semiconductor material having a mesh parameter different from that of the material of the first layer 4.
    When the first semiconductor layer 4 is based on silicon, the second semiconductor layer 6 may be provided based on silicon germanium (Sii-xGex with x for example between 20 and 50%). In this case, during epitaxial growth, the silicon germanium tends to follow the silicon mesh parameter, resulting in a layer of Sii-xGex compressive stress.
    Preferably, the thickness e 1 of the first semiconductor layer 4 is chosen to be less than a critical thickness of plastic relaxation. This critical thickness depends in particular on the stress level of the second semiconductor layer 6, this level itself being dependent in particular on the thickness β2 of the second semiconductor layer 6 and the mesh parameter of the material constituting it. When the second semiconductor layer 6 is based on Sii-xGex, the critical thickness below which the thickness ei of the superficial semiconductor layer 4 is chosen depends on the concentration of Germanium in the second semiconductor layer. For example, it is possible to provide a first semiconductor layer 4 made of silicon with a thickness ei of less than 10 nm when the second semiconductor layer 6 is made of Sii-xGex with x of the order of 0.20. The thickness e 1 of the second semiconductor layer 6 may be greater than e 1 and preferably as high as possible while remaining less than a critical thickness of plastic relaxation hc as evoked for example in the document entitled: "Critical thickness for plastic relaxation of SiGe by Hartmann et al. Journal of Applied Physics 2011. For example, when the second semiconductor layer 6 is Sii-xGex, its thickness may be of the order of 20 nm.
    FIG. 1A shows a step of forming a mask 10 for implantation on the second semiconductor layer 6.
    This implantation mask 10 is configured to protect certain regions of the second semiconductor layer 6 during a subsequent ion implantation step. The material and the thickness of the mask 10 implanted are adapted according to the implantation conditions and in particular the dose, energy, species considered for this implantation. According to one example, an etching mask 10 is formed by etching a W layer of thickness of the order of 25 nm deposited on a layer of 3 nm of SiC> 2. The layer in which the block or blocks of the mask 10 are made can be etched according to an AI2O3 hard mask made by ALD ("Atomic Layer Deposition") type deposition through openings of a co-polymer-based masking to blocks. The use of such masking can in particular make it possible to produce a mask 10 with implantation whose blocks have a homogeneous size and are evenly distributed on the second semiconductor layer 6.
    The mask 10 to be implanted may be formed of several blocks 10a, 10b, 10c, with a distribution symmetry of the blocks 10a, 10b, 10c relative to a given plane P, passing through the second semiconductor layer 6 and by least one masking block, the given plane P being orthogonal to a main plane of the substrate 1. By "main plane" of the substrate is meant here and throughout the description a plane passing through the substrate and which is parallel to the plane [O; x; y] orthogonal reference [O; x; there; z] given in Figure IA. In the example of FIG. 1A, the given plane P of symmetry is a plane passing through a first masking block 10a and separating two equal portions of this first block 10a.
    The blocks 10a, 10b, 10c forming the mask 10 are distributed in a constant pitch in at least one direction parallel to the main plane of the substrate 1. Thus, in the example of FIG. 1A, the blocks 10a, 10b, 10c are arranged so that a first minimum distance Dmin between the first block 10a and the second block 10b next to the first block 10a is equal to a minimum distance D2min between the first block 10a and the third block 10b adjacent to the first block 10a, Dlmin, D2min being equal to d, with d which can be for example of the order of 1 to 4 times the length of the blocks 10a, 10b, 10c, this length being measured parallel to the axis y in Figure IA.
    According to an exemplary embodiment, the blocks 10a, 10b, 10c may be provided with a length of the order of 1 to 3 times the thickness ei of the second semiconductor layer 6. This length is measured parallel to the axis x in Figure IA.
    The blocks 10a, 10b, 10c can also be formed with a width equal to or substantially equal to their length. The width of the blocks is here measured parallel to the axis y in FIG.
    Advantageously, among the blocks 10a, 10b, 10c of the mask 10 at least one block 10a is arranged facing a region 4a of the first semiconductor layer 4 in which a transistor channel structure is provided.
    Then, the first semiconductor layer 4 and certain zones 6 'of the semiconductor layer 6 which are not protected by the mask 10 are rendered amorphous.
    For this purpose, inclined ion implantations are carried out, that is to say such that the ion beam achieves a non-zero angle α, also called "tilt", with a normal n at the main plane of the substrate 1. Regions 6a, 6b, 6c, of the semiconductor layer 6 arranged under the blocks 10a, 10b, 10c of the mask 10 and protected by the latter are not rendered amorphous.
    The shape of the blocks 10a, 10b, 10c of the mask 10 may depend on the number of implantations performed. In one case, for example, where the blocks 10a, 10b, 10c are of equal width and length, it is possible to carry out implantations according to four different quadrants, in other words according to four different orientations of the ion beam.
    FIG. 1B illustrates an embodiment of at least two implantations inclined and symmetrical to one another with respect to the given plane P. FIG. 1C illustrates an implementation of at least two other implantations inclined and symmetrical to one another with respect to another plane P '. The plane P 'is orthogonal to the main plane of the substrate and to the given plane P. By way of example, in a case where the semiconductor layer 6 is a 20 nm layer of Sii-xGex with x equal to 20%, while the first semiconductor layer 4 is made of silicon and has a thickness of 10 nm, and that the mask 10 in HfC> 2 has a thickness of the order of 10 nm, it is possible to perform the amorphization step by means of implantations of Si, in a tilt of 20 °, a dose between 1.5 and 3x1014 at / cm2 an energy of between 20 and 30 keV.
    This amorphization makes it possible to obtain a relaxation of the regions 6a, 6b, 6c of the semiconductor layer 6. At the end of the amorphization, an arrangement of the regions 6a, 6b, 6c is obtained whose crystalline structure has been preserved. which follows that of the blocks 10a, 10b, 10c of the mask 10 to implantation.
    The implant mask 10 can then be removed. For example, when this mask 10 is W on S1O2, the shrinkage can be achieved using hydrogen peroxide (H2O2) and then hydrofluoric acid (HF).
    Then, the first semiconductor layer 4 and the amorphous zones 6 'of the superficial layer 6 are recrystallized by using the regions 6a, 6b, 6c whose crystal structure has been preserved as starting zones of fronts. recrystallization. FIG. 1D gives schematically and by means of arrows the direction of propagation of the recrystallization fronts.
    The recrystallization is carried out using at least one thermal annealing. By way of example, in a case where the semiconductor layer 6 is a 20 nm layer of
    Sii-xGex with x equal to 20%, while the first semiconductor layer 4 is made of silicon and has a thickness of 10 nm, an annealing of at least 2 minutes at a temperature of the order of 600 ° C. to be done.
    During recrystallization, the material of the regions 6a, 6b, 6c, for example Sii-xGex, imposes its mesh parameter to that of the first semiconductor layer 4, which is then stressed. When the first semiconductor layer 4 is based on Si, it is possible to obtain a layer 4 of silicon forced on insulator.
    Due to the arrangement of the crystalline regions 6a, 6b, 6c with respect to the areas made amorphous, it is possible to limit any crystalline crystal rotation phenomena, which ultimately results in a recrystallized semiconductor material of good quality. improved and in particular of more uniform crystalline orientation.
    FIG. 1E represents the stack of semiconductor layers 4, 6 once the recrystallization has been carried out. In this figure, lines in broken lines Z1, Z2 correspond to areas where the recrystallization fronts meet.
    A region 4a of the first semiconductor layer 4 in which a transistor channel region is provided is thus as far as possible away from the recrystallization fronts meeting zones, which can make it possible to implement a transistor with improved electrical performance. .
    Then, the second semiconductor layer 6 is removed. This removal can be performed by selective etching with respect to the material of the first semiconductor layer 4. For example, the selective etching of the second semiconductor layer and -conductor 6 when Sii-xGex and disposed on a layer 4 of Si, can be carried out using a mixture of acetic acid, hydrogen peroxide, and hydrofluoric acid. At the end of this withdrawal, a substrate of semiconductor type is obtained constrained on insulator as illustrated in Figure 1F and from which a microelectronic device can be realized.
    FIG. 2 shows a transistor structure T provided with a channel structure provided in the region 4a of the first semiconductor layer 4 which is the furthest away from the zones II, 22 where the recrystallization fronts meet.
    A variant of the embodiment previously described provides for producing a mask 100 with implantation formed this time of blocks 100a, 100b, 100c having a cylinder shape whose base extends parallel to the main plane of the substrate 1.
    Such a mask 100 is shown in Figure 3 in plan view.
    The mask 100 also has a symmetrical arrangement if we consider a plane P of symmetry orthogonal to the main plane of the substrate and passing through at least one block 100a. This mask 100 may be formed by depositing a layer through a masking in a block copolymer material. Such a material is able to self-organize into a plane hexagonal network of cylinders of substantially circular or polygonal section in a matrix. Such a material makes it possible to obtain a good homogeneity of the patterns of the masking and a distribution according to a constant pitch. The masking material may be in particular a diblock copolymer, one of which forms the cylinders and the other polymer forms a matrix. The diblock copolymer material may be for example one of: PS-PMMA (for polystyrene-poly (methyl methacrylate)), PS-PVP (for polystyrene-polyvinylpyrrolidone), PS-PEO (for "polystyrene polyethylene oxide). The masking pattern formation step includes selectively removing the rolls from the die. In one case, for example, where the rolls are PMMA-based in a PS matrix, shrinkage can be achieved by a method comprising immersion in an acetic acid bath for a period of several minutes, followed by exposure to a plasma of argon and oxygen.
    Another variant of the previously described embodiment is illustrated in FIGS. 4A-4C. This time, an implanted mask 110 is produced comprising parallelepiped-shaped blocks 110a, 110b, 110c which extend in the direction of their length, parallel to the main plane of the substrate 1.
    Such a mask 110 is shown in FIG. 4A in plan view. The mask 110 has parallelepipedal blocks also has a symmetrical arrangement with respect to a plane P of symmetry orthogonal to the main plane of the substrate and passing through the blocks 110a, 110b, 110c. The blocks 110a, 110b, 110c of the mask are arranged facing regions 4a, 4b, 4c of the first semiconductor layer 4 provided respectively to accommodate channel regions of transistors. Advantageously, these blocks 110a, 110b, 110c have a pattern similar to that provided for grids 41, 42, 43 of transistors Τι, Ï2, T3 intended to be made on regions 4a, 4b, 4c of the first semiconductor layer 4.
    Thus, in this example, a block 110a of the mask extends facing the entire region 4a in which the channel of the transistor Ti is provided.
    Then inclined ion implantations are carried out in order to achieve the amorphization of the first layer 4 and zones 6 'of the second layer. In this example, the amorphization can be carried out using implantations carried out on two different quadrants, in other words, as illustrated in FIG. 4B, using at least two inclined and symmetrical implantations. one of the other with respect to a plane P '. This plane P 'is orthogonal to the main plane of the substrate as well as to the plane P of symmetry of the mask 110.
    After this amorphization, the recrystallization steps are carried out so as to constrain the first semiconductor layer 4. By the arrangement of the mask 110 and the shape of these blocks 110a, 110b, 110c, it is possible, after recrystallization, obtaining a first semiconductor layer 4 in uniaxial stress in a direction parallel to the main plane of the substrate and orthogonal to that in which the blocks 110a, 110b, 110c of the mask 110 extend.
    Mask removal steps 110, removal of the second semiconductor layer 6 are also implemented.
    FIG. 4C illustrates the subsequent realization of transistors Τι, T2, T3 on regions 4a, 4b, 4c of the first semiconductor layer 4 opposite which the blocks 100a, 100b, 100c of the mask were arranged. The arrangement of the respective channel regions 4a, 4b, 4c of the transistors Τι, T2, T3 is provided outside the zones where the recrystallization fronts symbolized by the lines II, 22 meet, these zones being in this example located at the level of source and drain blocks. This avoids deteriorating the performance of the channels of the transistors Τι, T2, T3.
    As an alternative to one or the other of the examples of processes previously described, provision can be made for producing the mask 10 for implantation in a constrained material, such as silicon nitride which is stressed in tension, in order to increase the transferred stress. during the recrystallization of the zones 6 'and the first semiconductor layer 4.
    According to another variant embodiment of one or the other of the examples described above, a second Sii-yGey layer is formed with y varying for example between y = 0.20 at its lower face, and y = 0.50 at the level below. from its upper face. "Lower" face means that in contact with the first semiconductor layer 4, while the so-called "upper" face is opposite to the lower face.
    The second Sii-yGeya layer therefore has a Germanium concentration gradient with a concentration of Germanium which increases as one moves away from the first semiconductor layer. This can make it possible to preserve crystalline regions having a high Germanium concentration under the blocks of the mask 10 following the amorphization step. Recrystallization can then be carried out using crystalline seeds having a high Germanium concentration in order to obtain an increased stress in the first semiconductor layer 4.
    A process according to the invention can be applied to other pairs of materials than silicon and silicon germanium. A different stack of semiconductor layers 4 and 6 can be provided. For example, it is possible to put a first Germanium-constrained semiconductor layer 4 while this time epitaxially growing a second semiconductor layer 6 made of a higher mesh parameter material such as, for example, GexSni-x. According to another example, a first strained semiconductor layer 4 in Gn-yAs constrained can be made by growing a second semiconductor layer 6 in lnzAli-zAs (with z> y).
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    A method of producing a structure comprising a layer of constrained semiconductor material, the method comprising the steps of: a) providing on a substrate (1) a stack comprising a first semiconductor layer (4) based on a first semiconductor material coated with a second semiconductor layer (6) based on a second semiconductor material having a mesh parameter different from that of the first semiconductor material, b) producing on the second semiconductor material semiconductor layer a mask (10) formed of one or more blocks (10a, 10b, 10c, 100a, 100b, 100c, 110a, 110b, 110c), the mask being symmetrical with respect to a plane (P) of symmetry passing through at least a first block (10a, 100a, 110a) of the mask (10), this plane being orthogonal to a main plane of the substrate, c) performing one or more implantations inclined with respect to a normal to the main plane of the substrate, so as to make the first layer amorphous semiconductor layer (6) and areas (6 ') of the second semiconductor layer (6) without amorphous rendering one or more regions (6a, 6b, 6c) of the second semiconductor layer protected by the mask and disposed respectively opposite the one or more mask blocks, d) recrystallizing the amorphous regions (6a, 6b, 6c) and the first semiconductor layer resulting in this first semiconductor layer is constrained.
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein the first block or blocks (10a) are arranged facing a first region (4a) of the first semiconductor layer (4) in which a transistor channel (Ti) is apt to be realized.
    [3" id="c-fr-0003]
    The method of claim 2, wherein the first block (10a) is a transistor gate pattern.
    [4" id="c-fr-0004]
    4. Method according to one of claims 1 to 3, wherein the mask (10) is formed of several identical blocks (10a, 10b, 10c, 100a, 100b, 100c, 110a, 110b, 110c) arranged in the plane ( P) of symmetry in a constant distribution pitch.
    [5" id="c-fr-0005]
    5. The method of claim 4 wherein the mask (10) is formed by depositing at least one layer through block copolymer-based masking.
    [6" id="c-fr-0006]
    6. Method according to one of claims 1 to 5, wherein at least one block (110a, 110b, 110c) of the mask (10) has a cylinder shape whose base extends over the second semiconductor layer ( 6).
    [7" id="c-fr-0007]
    7. Method according to one of claims 1 to 6, wherein one or more blocks (110a, 110b, 110c) of the mask (10) have a parallelepipedal shape which extends parallel to the main plane of the substrate and orthogonal to the plane (P) symmetry.
    [8" id="c-fr-0008]
    8. Method according to one of claims 1 to 7, further comprising after the recrystallization step: a step of removing the second semiconductor layer (6).
    [9" id="c-fr-0009]
    The method according to claim 8, further comprising, after the step of removing the second semiconductor layer (6), forming a transistor (T) whose gate is arranged facing the first region ( 4a) and whose channel extends entirely into the first region.
    [10" id="c-fr-0010]
    10. Method according to one of claims 1 to 9, wherein the first semiconductor layer (3) is silicon, the second semiconductor layer (6) is silicon germanium.
    [11" id="c-fr-0011]
    11. The method of claim 10, wherein the second semiconductor layer (6) has a germanium concentration gradient.
    [12" id="c-fr-0012]
    12. A method of forming a transistor comprising the implementation of a method according to one of claims 1 to 11.
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    同族专利:
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    EP2840594A2|2013-08-09|2015-02-25|Commissariat à l'Énergie Atomique et aux Énergies Alternatives|Recrystallisation of blocks with source and drain by the top|
    FR2971618B1|2011-02-11|2015-07-31|Commissariat Energie Atomique|METHOD FOR OBTAINING A NETWORK OF NANOMETERIC PLOTS|FR3051970B1|2016-05-25|2020-06-12|Commissariat A L'energie Atomique Et Aux Energies Alternatives|REALIZATION OF A CHANNEL STRUCTURE FORMED OF A PLURALITY OF CONSTRAINED SEMICONDUCTOR BARS|
    FR3088480B1|2018-11-09|2020-12-04|Commissariat Energie Atomique|BONDING PROCESS WITH ELECTRONICALLY STIMULATED DESORPTION|
    FR3091619B1|2019-01-07|2021-01-29|Commissariat Energie Atomique|Healing process before transfer of a semiconductor layer|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1558482A|FR3041146B1|2015-09-11|2015-09-11|METHOD FOR TENSIONING A SEMICONDUCTOR FILM|
    FR1558482|2015-09-11|FR1558482A| FR3041146B1|2015-09-11|2015-09-11|METHOD FOR TENSIONING A SEMICONDUCTOR FILM|
    US15/260,767| US9704709B2|2015-09-11|2016-09-09|Method for causing tensile strain in a semiconductor film|
    EP16188202.2A| EP3142152B1|2015-09-11|2016-09-09|Method for tensioning a semiconductor film|
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